1. Field of the Invention
The present invention relates to leadframes and semiconductor chip packages, and particularly to a leadframe and a semiconductor chip package having high lead count.
2. Description of the Prior Art
The major trends and goals in the electronic industry have been to achieve high integration, low power consumption, large memory capacity and high processing speed in integrated circuits on a semiconductor chip. High integration and large memory capacity generally require a semiconductor chip having a large number of I/O (Input/Output) pads. Designing compact leadframes and packages for these semiconductor chips is difficult because of the number of leads. While the size of the semiconductor chip package should be minimized, the size and number of I/O pads of a chip such as a random access memory (RAM) chip increases as the memory capacity of the chip increases. The semiconductor chip package thus requires a large mounting area for the chip and a larger perimeter for adequate separation of leads.
FIG. 1 is a top plan view of a semiconductor chip package 10 that is a quad flat package (QFP) with leads 12 having a lead count of 208. The semiconductor chip package 10 has a lead pitch a of 0.5 mm, and each side of the package has a length b of 28.0 mm. The lead pitch a is the distance between center lines of two adjacent leads 12.
The lead count of a semiconductor chip package such as the package 10 can be increased by increasing the external dimensions of the package body or decreasing the lead pitch. I For example, if the length b of the package body is increased to 32 mm and the lead pitch remains 0.5 mm, the lead count of the semiconductor chip package can be increased 240 lead counts. However, increasing the size of a semiconductor chip package is undesirable. Accordingly, decreasing the pitch a of leads 12 may be considered. For example, a semiconductor chip package with a lead count of 256 and an external length of 28 mm requires the lead pitch a of about 0.4 mm. The narrower pitch may result in shorts between adjacent leads. In addition, decreasing the lead pitch a generally requires decreasing the width of leads 12. If the width of leads 12 decreases, the leads 12 are more easily bent during the handling of the semiconductor chip package 10.
Another method for accommodating a large number of external terminals is to employ a different package architecture such as a ball grid array package. Ball grid array packages have a large number of solder bumps, instead of outer leads, as the external terminals. For the same number of external terminals, the solder bump pitch in a ball grid array package can be larger than the outer lead pitch of the package 10. However, the ball grid packages are more expensive than the plastic package such as package 10 of FIG. 1.
FIG. 2 is a top plan view of a semiconductor chip package 20 disclosed in Japanese Patent Laid-Open No. 62-83626, which is incorporated herein by reference in its entirety. FIGS. 2A and 2B illustrate possible variants of the lead configurations in the semiconductor chip package of FIG. 2. In package 20, sides 26 are bow-shaped to increase the perimeter and decrease the area of a package body 24 of package 20, relative to the rectangular area A.
However, contrary to the disclosure in Japanese Patent Laid-Open No. 6-283626, the number of leads 22 cannot be increased without expanding the external dimensions of the package body 24. As shown in FIG. 2A, if the leads 22a extend from the package body parallel to each other, the spacing and the number of leads 22a are the same as those of the conventional example shown in FIG. 1 which has a square planar shape matching the rectangular area A. Accordingly, although the side 26a is longer, the number of leads 22a cannot be increased without reducing lead pitch.
Referring to FIG. 2B, if the leads 22b extend in directions perpendicular to a side 26b, the pitch axe2x80x2 at the ends of the leads 22b, differs from the pitch bxe2x80x2 at side 26b. Accordingly, the number of leads 22b cannot be increased without reducing the lead pitch axe2x80x2. The lead pitch axe2x80x2 should be sufficient to avoid problems such as short circuiting during a soldering process in which attaches the semiconductor chip package 20 to a printed circuit board. Again, although the side 26b is longer, the lead pitch axe2x80x2 decreases when the number of leads 22b increases. Therefore, it is impossible to increase the number of leads 22b without decreasing the lead pitch (axe2x80x2).
An aspect of the present invention provides a semiconductor chip package that can accommodate many outer leads in a relatively small package. The package includes a package body and outer leads along the perimeter of the package body. The package body has cutout or concave portions to increase the perimeter of the body and the number of outer leads without increasing the package footprint. For example, the package can have a QFP outline with cutout portions on the sides of the QFP outline. The package can have an SOP outline with concave portions on two opposite sides of the SOP outline.